mirror of
https://github.com/johndoe6345789/metabuilder.git
synced 2026-04-24 13:54:57 +00:00
86 lines
2.7 KiB
Python
86 lines
2.7 KiB
Python
import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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sys.path.insert(0, str(ROOT))
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import pytest
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from boardforge import Board, DRCError
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def test_drc_pad_clearance_warning():
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board = Board(width=5, height=5)
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board.set_layer_stack(["GTL", "GBL"])
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c1 = board.add_component("A", ref="U1", at=(0, 0))
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c1.add_pin("P", dx=0, dy=0)
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c1.add_pad("P", dx=0, dy=0, w=1, h=1)
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c2 = board.add_component("B", ref="U2", at=(0.6, 0))
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c2.add_pin("P", dx=0, dy=0)
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c2.add_pad("P", dx=0, dy=0, w=1, h=1)
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with pytest.raises(DRCError) as excinfo:
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board.design_rule_check(min_clearance=0.7)
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assert any("Pad clearance" in w for w in excinfo.value.warnings)
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def test_drc_trace_width_warning():
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board = Board(width=5, height=5)
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board.set_layer_stack(["GTL", "GBL"])
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c1 = board.add_component("A", ref="U1", at=(0, 0))
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c1.add_pin("P", dx=0, dy=0)
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c1.add_pad("P", dx=0, dy=0, w=1, h=1)
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c2 = board.add_component("B", ref="U2", at=(4, 0))
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c2.add_pin("P", dx=0, dy=0)
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c2.add_pad("P", dx=0, dy=0, w=1, h=1)
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board.trace(c1.pin("P"), c2.pin("P"), width=0.1)
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with pytest.raises(DRCError) as excinfo:
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board.design_rule_check(min_trace_width=0.15)
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assert any("width" in w for w in excinfo.value.warnings)
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def test_export_raises_on_drc_failure(tmp_path):
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board = Board(width=5, height=5)
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board.set_layer_stack(["GTL", "GBL"])
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c1 = board.add_component("A", ref="U1", at=(0, 0))
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c1.add_pin("P", dx=0, dy=0)
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c1.add_pad("P", dx=0, dy=0, w=1, h=1)
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c2 = board.add_component("B", ref="U2", at=(0.6, 0))
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c2.add_pin("P", dx=0, dy=0)
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c2.add_pad("P", dx=0, dy=0, w=1, h=1)
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zip_path = tmp_path / "out.zip"
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with pytest.raises(DRCError):
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board.export_gerbers(zip_path)
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def test_drc_uses_layer_service_defaults():
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board = Board(width=5, height=5)
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board.set_layer_stack(["GTL", "GBL"])
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c1 = board.add_component("A", ref="U1", at=(0, 0))
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c1.add_pin("P", dx=0, dy=0)
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c1.add_pad("P", dx=0, dy=0, w=1, h=1)
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c2 = board.add_component("B", ref="U2", at=(4, 0))
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c2.add_pin("P", dx=0, dy=0)
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c2.add_pad("P", dx=0, dy=0, w=1, h=1)
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board.trace(c1.pin("P"), c2.pin("P"), width=0.1)
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with pytest.raises(DRCError) as excinfo:
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board.design_rule_check()
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assert any("width" in w for w in excinfo.value.warnings)
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def test_via_rules_enforced():
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board = Board(width=5, height=5)
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board.set_layer_stack(["GTL", "GBL"])
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board.add_via(1, 1, diameter=0.3, hole=0.2)
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board.add_via(1.2, 1, diameter=0.3, hole=0.2)
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with pytest.raises(DRCError) as excinfo:
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board.design_rule_check()
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assert any("Via" in w for w in excinfo.value.warnings)
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